92 search results - page 3 / 19 » Distributed Synthesis for Well-Connected Architectures |
ICCAD
2005
IEEE
13 years 11 months ago
2005
IEEE
— This paper presents an architecture and a wrapper synthesis approach for the design of multi-clock systems-on-chips. We build upon the initial work on multi-clock latency-insen...
VLSID
2002
IEEE
14 years 6 months ago
2002
IEEE
In this paper, we present a functional partitioning method for low power real-time distributed embedded systems whose constituent nodes are systems-on-a-chip (SOCs). The systemlev...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
In deep submicron technology, wire delay is no longer negligible and is gradually dominating the system latency. Some state-of-the-art architectural synthesis flows adopt the distr...
ICCAD
1998
IEEE
13 years 10 months ago
1998
IEEE
Designers of distributed embedded systems face many challenges in determining the appropriate tradeoffs to make when defining a system architecture or retargeting an existing desi...
DAC
2000
ACM
14 years 6 months ago
2000
ACM
A main advantage of control composition with modal processes [4] is the enhanced retargetability of the composed behavior over a wide variety of target architectures. Unlike previ...