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ERSA
2006
186views Hardware» more  ERSA 2006»
13 years 6 months ago
The Case for High Level Programming Models for Reconfigurable Computers
In this paper we first outline and discuss the issues of currently accepted computational models for hybrid CPU/FPGA systems. Then, we discuss the need for researchers to develop ...
David L. Andrews, Ron Sass, Erik Anderson, Jason A...
PARLE
1991
13 years 8 months ago
FORK: A High-Level Language for PRAMs
We present a new programming language designed to allow the convenient expression of algorithms for a parallel random access machine (PRAM). The language attempts to satisfy two p...
Torben Hagerup, Arno Schmitt, Helmut Seidl
IPPS
2007
IEEE
13 years 11 months ago
Coordinating Data Parallel SAC Programs with S-Net
We propose a two-layered approach for exploiting different forms of concurrency in complex systems: We specify computational components in our functional array language SaC, whic...
Clemens Grelck, Sven-Bodo Scholz, Alexander V. Sha...
IPPS
2007
IEEE
13 years 11 months ago
A Study of Design Efficiency with a High-Level Language for FPGAs
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
Zain-ul-Abdin, Bertil Svensson
CCGRID
2010
IEEE
13 years 6 months ago
A High-Level Interpreted MPI Library for Parallel Computing in Volunteer Environments
Idle desktops have been successfully used to run sequential and master-slave task parallel codes on a large scale in the context of volunteer computing. However, execution of messa...
Troy P. LeBlanc, Jaspal Subhlok, Edgar Gabriel