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» Distributed simulation for structural VHDL netlists
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EURODAC
1994
IEEE
129views VHDL» more  EURODAC 1994»
13 years 9 months ago
Distributed simulation for structural VHDL netlists
: This article describes the current state of the project to develop distributed simulation. The reader will have
David B. Bernstein, Werner van Almsick, Wilfried D...
IPPS
2002
IEEE
13 years 10 months ago
Overview of Hydra: A Concurrent Language for Synchronous Digital Circuit Design
Hydra is a computer hardware description language that integrates several kinds of software tool (simulation, netlist generation and timing analysis) within a single circuit speci...
John O'Donnell
IPPS
1996
IEEE
13 years 9 months ago
A New Approach to Pipeline FFT Processor
A new VLSI architecture for real-time pipeline FFT processor is proposed. A hardware oriented radix-22 algorithm is derived by integrating a twiddle factor decomposition technique ...
Shousheng He, Mats Torkelson
EURODAC
1994
IEEE
127views VHDL» more  EURODAC 1994»
13 years 9 months ago
Optimal equivalent circuits for interconnect delay calculations using moments
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...
Sudhakar Muddu, Andrew B. Kahng