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ISCA
1991
IEEE
110views Hardware» more  ISCA 1991»
13 years 8 months ago
Dynamic Base Register Caching: A Technique for Reducing Address Bus Width
When address reference streams exhibit high degrees of spatial and temporal locality, many of the higher order address lines carry redundant information. By caching the higher ord...
Matthew K. Farrens, Arvin Park
VLSID
2003
IEEE
108views VLSI» more  VLSID 2003»
14 years 5 months ago
A Low Power-Delay Product Page-Based Address Bus Coding Method
The working-zone encoding (WZE) method employing locality of memory reference was previously proposed to reduce address bus switching activity. This paper presents an encoding met...
Chi-Ming Tsai, Guang-Wan Liao, Rung-Bin Lin
CASES
2005
ACM
13 years 7 months ago
A post-compilation register reassignment technique for improving hamming distance code compression
Code compression is a field where compression ratios between compiler-generated code and subsequent compressed code are highly dependent on decisions made at compile time. Most op...
Montserrat Ros, Peter Sutton
EMSOFT
2004
Springer
13 years 10 months ago
Binary translation to improve energy efficiency through post-pass register re-allocation
Energy efficiency is rapidly becoming a first class optimization parameter for modern systems. Caches are critical to the overall performance and thus, modern processors (both hig...
Kun Zhang, Tao Zhang, Santosh Pande
MICRO
2008
IEEE
111views Hardware» more  MICRO 2008»
13 years 11 months ago
Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer
It is well recognized that LRU cache-line replacement can be ineffective for applications with large working sets or non-localized memory access patterns. Specifically, in lastle...
Livio Soares, David K. Tam, Michael Stumm