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» Dynamic Branch Prediction for a VLIW Processor
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ISCA
2002
IEEE
95views Hardware» more  ISCA 2002»
13 years 10 months ago
Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor
This paper presents the Alpha EV8 conditional branch predictor. The Alpha EV8 microprocessor project, canceled in June 2001 in a late phase of development, envisioned an aggressiv...
André Seznec, Stephen Felix, Venkata Krishn...
ISCAPDCS
2003
13 years 7 months ago
N-Tuple Compression: A Novel Method for Compression of Branch Instruction Traces
Branch predictors and processor front-ends have been the focus of a number of computer architecture studies. Typically they are evaluated separately from other components using tr...
Aleksandar Milenkovic, Milena Milenkovic, Jeffrey ...
CORR
2006
Springer
109views Education» more  CORR 2006»
13 years 5 months ago
On Conditional Branches in Optimal Decision Trees
The decision tree is one of the most fundamental ing abstractions. A commonly used type of decision tree is the alphabetic binary tree, which uses (without loss of generality) &quo...
Michael B. Baer
ISPASS
2009
IEEE
14 years 17 days ago
Accurately approximating superscalar processor performance from traces
Trace-driven simulation of superscalar processors is particularly complicated. The dynamic nature of superscalar processors combined with the static nature of traces can lead to l...
Kiyeon Lee, Shayne Evans, Sangyeun Cho
ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
13 years 10 months ago
Understanding the backward slices of performance degrading instructions
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
Craig B. Zilles, Gurindar S. Sohi