4 search results - page 1 / 1 » Dynamic Compaction in SAT-Based ATPG |
ATS
2009
IEEE
13 years 11 months ago
2009
IEEE
SAT-based automatic test pattern generation has several advantages compared to conventional structural procedures, yet often yields too large test sets. We present a dynamic compa...
DATE
1999
IEEE
13 years 9 months ago
1999
IEEE
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
ICCAD
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper presents two new algorithms, Redundant Vector Elimination(RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under th...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
Deterministic observation and random excitation of fault sites during the ATPG process dramatically reduces the overall defective part level. However, multiple observations of eac...