41 search results - page 2 / 9 » Dynamic Partial Reconfigurable FIR Filter Design |
FDL
2004
IEEE
13 years 9 months ago
2004
IEEE
This paper presents a new approach to design embedded systems based on dynamic partial reconfigurable FPGAs. The approach is intended to allow designing of systems with runtime re...
SAMOS
2005
Springer
13 years 11 months ago
2005
Springer
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. P...
CEC
2008
IEEE
14 years 15 days ago
2008
IEEE
— In this paper, swarm and evolutionary algorithms have been applied for the design of digital filters. Particle swarm optimization (PSO) and differential evolution particle swar...
CDES
2006
13 years 7 months ago
2006
Abstract-- Digital signal processing (DSP) is used to perform filtering, decimation and down conversion in common communications systems, like in oversampling analog to digital con...
DAGSTUHL
2006
13 years 7 months ago
2006
We present an FPGA-based reconfigurable platform called Erlangen Slot Machine (ESM). The main advantages of this platform are: First, the possibility for each module to access peri...