16 search results - page 2 / 4 » Dynamic and Leakage Power Minimization with Loop Voltage Sch... |
ISLPED
2004
ACM
13 years 10 months ago
2004
ACM
Traditionally, dynamic voltage scaling (DVS) techniques have focused on minimizing the processorenergy consumption as opposed to the entire system energy consumption. The slowdown...
ISSS
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper presents a real-time task scheduling technique with a variable voltage processor which can vary its supply voltage dynamically. Using such a processor, running tasks wi...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
In a parallel system with multiple CPUs, one of the key problems is to assign loop iterations to processors. This problem, known as the loop scheduling problem, has been studied i...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
– Reducing power consumption through high-level synthesis has attracted a growing interest from researchers due to its large potential for power reduction. In this work we study ...