35 search results - page 7 / 7 » Dynamic configuration steering for a reconfigurable supersca... |
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
PACS
2000
Springer
13 years 9 months ago
2000
Springer
Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue ...
IJCAI
1997
13 years 6 months ago
1997
This paper describes an evolvable hardware (EHW) system for generalized neural network learning. We have developed an ASIC VLSI chip, which is a building block to configure a scal...
ICCAD
2009
IEEE
13 years 3 months ago
2009
IEEE
Multi-core processors have become an integral part of mainstream high performance computer systems. In parallel, exponentially increasing power density and packaging costs have ne...
ASPLOS
2008
ACM
13 years 7 months ago
2008
ACM
Future multicore processors will be more susceptible to a variety of hardware failures. In particular, intermittent faults, caused in part by manufacturing, thermal, and voltage v...