— Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architec...
3D stacked circuits reduce communication delay in multicore system-on-chips (SoCs) and enable heterogeneous integration of cores, memories, sensors, and RF devices. However, vertic...
Mohamed M. Sabry, Ayse Kivilcim Coskun, David Atie...
Recently, processor power density has been increasing at an alarming rate resulting in high on-chip temperature. Higher temperature increases current leakage and causes poor relia...
Power density continues to increase exponentially with each new technology generation, posing a major challenge for thermal management in modern processors. Much past work has exa...
- Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact...
Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Re...