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» Dynamic zero compression for cache energy reduction
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MICRO
2000
IEEE
122views Hardware» more  MICRO 2000»
13 years 9 months ago
Dynamic zero compression for cache energy reduction
Dynamic Zero Compression reduces the energy required for cache accesses by only writing and reading a single bit for every zero-valued byte. This energy-conscious compression is i...
Luis Villa, Michael Zhang, Krste Asanovic
EMSOFT
2004
Springer
13 years 10 months ago
Binary translation to improve energy efficiency through post-pass register re-allocation
Energy efficiency is rapidly becoming a first class optimization parameter for modern systems. Caches are critical to the overall performance and thus, modern processors (both hig...
Kun Zhang, Tao Zhang, Santosh Pande
ICCD
2001
IEEE
84views Hardware» more  ICCD 2001»
14 years 1 months ago
Static Energy Reduction Techniques for Microprocessor Caches
Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of increased static energy consumption ...
Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, S...
ARCS
2006
Springer
13 years 8 months ago
Dynamic Dictionary-Based Data Compression for Level-1 Caches
Abstract. Data cache compression is actively studied as a venue to make better use of onchip transistors, increase apparent capacity of caches, and hide the long memory latencies. ...
Georgios Keramidas, Konstantinos Aisopos, Stefanos...
MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
13 years 4 months ago
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
Nam Sung Kim, Krisztián Flautner, David Bla...