40 search results - page 3 / 8 » Dynamic zero compression for cache energy reduction |
ISLPED
2010
ACM
13 years 6 months ago
2010
ACM
The on-chip memory is a dominant source of power and energy consumption in modern and future processors. This paper explores the use of a new emerging non-volatile memory technolo...
ICCD
2004
IEEE
14 years 2 months ago
2004
IEEE
Dynamic address compression schemes that exploit address locality can help reduce both address bus energy and cost simultaneously with only a small performance penalty. In this wo...
ISCAS
2002
IEEE
13 years 10 months ago
2002
IEEE
In this paper, we present two methods to reduce leakage energy by dynamically resizing the cache during program execution. The first method monitors the miss rate of the individua...
ASPDAC
2009
ACM
13 years 3 months ago
2009
ACM
The proliferation of Chip Multiprocessors (CMPs) has led to the integration of large on-chip caches. For scalability reasons, a large on-chip cache is often divided into smaller ba...
MICRO
1999
IEEE
13 years 10 months ago
1999
IEEE
Increasing levels of microprocessor power dissipation call for new approaches at the architectural level that save energy by better matching of on-chip resources to application re...