16 search results - page 1 / 4 » Dynamically configurable security for SRAM FPGA bitstreams |
IJES
2006
13 years 4 months ago
2006
This paper proposes a solution to improve the security of SRAM FPGAs through bitstream encryption. This proposition is distinct from other works because it uses the latest capabil...
FPT
2005
IEEE
13 years 10 months ago
2005
IEEE
SRAM FPGAs are vulnerable to security breaches such as bitstream cloning, reverse-engineering, and tampering. Bitstream encryption and authentication are two most effective and pr...
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
Soft errors that change configuration bits of an SRAM based FPGA modify the functionality of the design. The proliferation of FPGA devices in various critical applications makes it...
FPL
2008
Springer
13 years 6 months ago
2008
Springer
In the context of FPGAs, system downgrade consists in preventing the update of the hardware configuration or in replaying an old bitstream. The objective can be to preclude a syst...
FPL
2008
Springer
13 years 6 months ago
2008
Springer
A high-speed and secure dynamic partial reconfiguration (DPR) system is realized with AES-GCM that guarantees both confidentiality and authenticity of FPGA bitstreams. In DPR syst...