35 search results - page 7 / 7 » Dynamically reconfigurable cache architecture using adaptive... |
TVLSI
2008
13 years 5 months ago
2008
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
AUSAI
2005
Springer
13 years 11 months ago
2005
Springer
This paper addresses the problem of scheduling jobs in soft real-time systems, where the utility of completing each job decreases over time. We present a utility-based framework fo...
IEEEPACT
2007
IEEE
13 years 11 months ago
2007
IEEE
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
CCR
2011
13 years 9 days ago
2011
Proliferation and innovation of wireless technologies require significant amounts of radio spectrum. Recent policy reforms by the FCC are paving the way by freeing up spectrum fo...
MASCOTS
2010
13 years 6 months ago
2010
Subtle implementation errors or mis-configurations in complex Internet services may lead to performance degradations without causing failures. These undiscovered performance anomal...