5 search results - page 1 / 1 » Edge-map: optimal performance driven technology mapping for ... |
ICCAD
1994
IEEE
13 years 8 months ago
1994
IEEE
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
DAC
2005
ACM
14 years 5 months ago
2005
ACM
This paper attempts to quantify the optimality of FPGA technology mapping algorithms. We develop an algorithm, based on Boolean satisfiability (SAT), that is able to map a small s...
ICCAD
2007
IEEE
14 years 1 months ago
2007
IEEE
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...
DAC
1993
ACM
13 years 8 months ago
1993
ACM
In this paper we study the area and depth trade-off in LUT based FPGA technology mapping. Starting from a depth-optimal mapping solution, we perform a number of depth relaxation o...