12 search results - page 2 / 3 » Effective Capacitance Macro-Modelling for Architectural-Leve... |
ISCAS
2008
IEEE
13 years 11 months ago
2008
IEEE
— The non-monotonic behavior of power/ground noise with respect to the rise time tr is investigated for an inductive power distribution network with a decoupling capacitor. A tim...
DAC
1999
ACM
14 years 6 months ago
1999
ACM
We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...
SOCC
2008
IEEE
13 years 11 months ago
2008
IEEE
— A distributed on-chip decoupling capacitor network is proposed in this paper to replace one large capacitor. A system of distributed on-chip decoupling capacitors is shown to p...
ISCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
In recent times, much attention has been devoted to power optimization for real-time systems, while guaranteeing that such systems meet their hard (or soft) scheduling deadlines. ...
PPOPP
2005
ACM
13 years 11 months ago
2005
ACM
Disk subsystem is known to be a major contributor to overall power consumption of high-end parallel systems. Past research proposed several architectural level techniques to reduc...