9 search results - page 1 / 2 » Effective Instruction Prefetching via Fetch Prestaging |
IPPS
2005
IEEE
13 years 10 months ago
2005
IEEE
As technological process shrinks and clock rate increases, instruction caches can no longer be accessed in one cycle. Alternatives are implementing smaller caches (with higher mis...
ISCA
1995
IEEE
13 years 8 months ago
1995
IEEE
Current trends in processor design are pointing to deeper and wider pipelines and superscalar architectures. The efficient use of these resources requires speculative execution, ...
HPCA
2005
IEEE
14 years 4 months ago
2005
IEEE
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
HPCA
2008
IEEE
14 years 4 months ago
2008
IEEE
Fetch gating mechanisms have been proposed to gate the processor pipeline to reduce the wasted energy consumption due to wrongpath (i.e. mis-speculated) instructions. These scheme...
ASPLOS
2004
ACM
13 years 10 months ago
2004
ACM
This paper introduces a compiler-orchestrated prefetching system as a unified framework geared toward ameliorating the gap between processing speeds and memory access latencies. ...