11 search results - page 1 / 3 » Effective ahead Pipelining of Instruction Block Address Gene... |
ISCA
2003
IEEE
13 years 10 months ago
2003
IEEE
On a N-way issue superscalar processor, the front end instruction fetch engine must deliver instructions to the execution core at a sustained rate higher than N instructions per c...
LCTRTS
2007
Springer
13 years 11 months ago
2007
Springer
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
HPCA
2004
IEEE
14 years 5 months ago
2004
IEEE
This paper focuses on generating efficient software pipelined schedules for in-order machines, which we call Converged Trace Schedules. For a candidate loop, we form a string of t...
IEEEPACT
2005
IEEE
13 years 10 months ago
2005
IEEE
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
ISCA
1995
IEEE
13 years 8 months ago
1995
IEEE
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...