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ISVLSI
2006
IEEE
88views VLSI» more  ISVLSI 2006»
13 years 11 months ago
Effects of Parameter Variations and Crosstalk Noise on H-Tree Clock Distribution Networks
— The effects of parameter variations and crosstalk noise on the clock signal propagating along an H-tree clock distribution network are investigated in this paper. In particular...
Itisha Chanodia, Dimitrios Velenis
ISCAS
2006
IEEE
98views Hardware» more  ISCAS 2006»
13 years 11 months ago
Effects of crosstalk noise on H-tree clock distribution networks
— With the transition to deep submicron technologies the density of on-chip interconnect lines has increased, together with the switching rate of the signals propagating along th...
Itisha Chanodia, Dimitrios Velenis
DATE
2003
IEEE
103views Hardware» more  DATE 2003»
13 years 10 months ago
Reduced Delay Uncertainty in High Performance Clock Distribution Networks
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
Dimitrios Velenis, Marios C. Papaefthymiou, Eby G....
ISQED
2007
IEEE
127views Hardware» more  ISQED 2007»
13 years 11 months ago
Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Ch...
DAC
1996
ACM
13 years 9 months ago
Optimal Clock Skew Scheduling Tolerant to Process Variations
1- A methodology is presented in this paper for determining an optimal set of clock path delays for designing high performance VLSI/ULSI-based clock distribution networks. This met...
José Luis Neves, Eby G. Friedman