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DAC
2004
ACM
13 years 9 months ago
Enabling energy efficiency in via-patterned gate array devices
In an attempt to enable the cost-effective production of lowand mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architecture...
R. Reed Taylor, Herman Schmit
FLAIRS
2001
13 years 7 months ago
A Computational Model for Portfolios of Cooperative Heterogeneous Algorithms for Discrete Optimization
Discrete optimization problemsarise throughout many real world domainsincluding planning, decision making, and search. NP-hardin general, these problems require novel approachesto...
Eugene Santos Jr.
EUROPAR
2000
Springer
13 years 9 months ago
Cache Remapping to Improve the Performance of Tiled Algorithms
With the increasing processing power, the latency of the memory hierarchy becomes the stumbling block of many modern computer architectures. In order to speed-up the calculations, ...
Kristof Beyls, Erik H. D'Hollander
CORR
2010
Springer
153views Education» more  CORR 2010»
13 years 6 months ago
Towards an Efficient Tile Matrix Inversion of Symmetric Positive Definite Matrices on Multicore Architectures
The algorithms in the current sequential numerical linear algebra libraries (e.g. LAPACK) do not parallelize well on multicore architectures. A new family of algorithms, the tile a...
Emmanuel Agullo, Henricus Bouwmeester, Jack Dongar...
DAC
2005
ACM
14 years 7 months ago
Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design
In many of embedded systems, particularly for those with high data computations, the delay of memory access is one of the major bottlenecks in the system's performance. It ha...
Jungeun Kim, Taewhan Kim