17 search results - page 1 / 4 » Efficient DC Fault Simulation of Nonlinear Analog Circuits |
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
Efficient dc fault simulation of nonlinear analog circuits is addressed in this paper. Two techniques, one-step relaxation and adaptive simulation continuation, are proposed. By on...
ICCAD
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper presents a novel concurrent fault simulator (called CONCERT) for nonlinear analog circuits. Three primary techniques in CONCERT, including fault ordering, state predict...
ATS
2009
IEEE
13 years 11 months ago
2009
IEEE
—A method of testing for parametric faults of analog circuits based on a polynomial representation of fault-free function of the circuit is presented. The response of the circuit...
ICCAD
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The s...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
The impact of parameter variations in integrated analog circuits is usually analyzed by Monte Carlo methods with a high number of simulation runs. Few approaches based on interval ...