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ISQED
2010
IEEE
137views Hardware» more  ISQED 2010»
13 years 2 months ago
Analysis of power supply induced jitter in actively de-skewed multi-core systems
This paper studies multi-core clock distribution using active deskewing methods. We propose an efficient methodology that uses Verilog-A to model PLLs, clock trees and power suppl...
Derek Chan, Matthew R. Guthaus
DAC
2010
ACM
13 years 5 months ago
Parallel multigrid preconditioning on graphics processing units (GPUs) for robust power grid analysis
Leveraging the power of nowadays graphics processing units for robust power grid simulation remains a challenging task. Existing preconditioned iterative methods that require inco...
Zhuo Feng, Zhiyu Zeng
IPSN
2007
Springer
13 years 11 months ago
MeshEye: a hybrid-resolution smart camera mote for applications in distributed intelligent surveillance
Surveillance is one of the promising applications to which smart camera motes forming a vision-enabled network can add increasing levels of intelligence. We see a high degree of i...
Stephan Hengstler, Daniel Prashanth, Sufen Fong, H...
ICCAD
2010
IEEE
158views Hardware» more  ICCAD 2010»
13 years 2 months ago
Novel binary linear programming for high performance clock mesh synthesis
Clock mesh is popular in high performance VLSI design because it is more robust against variations than clock tree at a cost of higher power consumption. In this paper, we propose ...
Minsik Cho, David Z. Pan, Ruchir Puri
GLVLSI
2009
IEEE
123views VLSI» more  GLVLSI 2009»
13 years 11 months ago
Power efficient tree-based crosslinks for skew reduction
Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutio...
Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G...