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ISQED
2010
IEEE

Analysis of power supply induced jitter in actively de-skewed multi-core systems

9 years 9 months ago
Analysis of power supply induced jitter in actively de-skewed multi-core systems
This paper studies multi-core clock distribution using active deskewing methods. We propose an efficient methodology that uses Verilog-A to model PLLs, clock trees and power supply variation in multi-core designs. Using the methodology, we compare four different de-skewing topologies (region-based, linear, ring, and a tree) for nominal performance and robustness to power supply variation. We conclude that under nominal conditions, the ring and line topologies are better with a large number of cores, but, when power supply is considered, the region topology is best. Keywords Multi-core, clock distribution, de-skewing
Derek Chan, Matthew R. Guthaus
Added 13 Feb 2011
Updated 13 Feb 2011
Type Journal
Year 2010
Where ISQED
Authors Derek Chan, Matthew R. Guthaus
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