279 search results - page 1 / 56 » Efficient Power Co-Estimation Techniques for System-on-Chip ... |
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
BWCCA
2010
12 years 12 months ago
2010
Network-on-Chip (NoC) architectures provide a good way of realizing efficient interconnections and largely alleviate the limitations of bus-based solutions. NoC has emerged as a so...
DSD
2008
IEEE
13 years 6 months ago
2008
IEEE
Platform-based design represents the most widely used approach to design System-On-Chip (SOC) applications. In this context, the Design Space Exploration (DSE) phase consists of o...
FDL
2005
IEEE
13 years 10 months ago
2005
IEEE
Although Moore’s Law enables a huge number of components to be integrated into a single chip, design methods that will allow system architects to put the components together to ...
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
—In this paper, we examine the design process of a Network on-Chip (NoC) for a high-end commercial System onChip (SoC) application. We present several design choices and focus on...