38 search results - page 1 / 8 » Efficient Techniques for Directed Test Generation Using Incr... |
VLSID
2009
IEEE
14 years 5 months ago
2009
IEEE
Functional validation is a major bottleneck in the current SOC design methodology. While specification-based validation techniques have proposed several promising ideas, the time ...
TCAD
2010
12 years 11 months ago
2010
Abstract--Functional verification is one of the major bottlenecks in system-on-chip design due to the combined effects of increasing complexity and lack of automated techniques for...
VLSID
2010
IEEE
13 years 2 months ago
2010
IEEE
Directed test generation is important for the functional verification of complex system-on-chip designs. SAT based bounded model checking is promising for counterexample generatio...
DAC
1998
ACM
14 years 5 months ago
1998
ACM
Abstract-Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model des...
SIGSOFT
2010
ACM
13 years 2 months ago
2010
ACM
Test suite augmentation techniques are used in regression testing to identify code elements affected by changes and to generate test cases to cover those elements. Our preliminary...