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» Efficient checker processor design
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IPPS
1998
IEEE
13 years 9 months ago
Benchmarking the Task Graph Scheduling Algorithms
The problem of scheduling a weighted directed acyclic graph (DAG) to a set of homogeneous processors to minimize the completion time has been extensively studied. The NPcompletene...
Yu-Kwong Kwok, Ishfaq Ahmad
ICPADS
1994
IEEE
13 years 9 months ago
Stochastic Modeling of Scaled Parallel Programs
Testingthe performance scalabilityof parallelprograms can be a time consuming task, involving many performance runs for different computer configurations, processor numbers, and p...
Allen D. Malony, Vassilis Mertsiotakis, Andreas Qu...
FPGA
1995
ACM
118views FPGA» more  FPGA 1995»
13 years 8 months ago
An SBus Monitor Board
During the development of computer peripherals which interface to the processor via the system bus it is often necessary to acquire the signals on the bus at the hardware level. I...
H. A. Xie, Kevin E. Forward, K. M. Adams, D. Leask
ICCAD
2009
IEEE
171views Hardware» more  ICCAD 2009»
13 years 3 months ago
A hybrid local-global approach for multi-core thermal management
Multi-core processors have become an integral part of mainstream high performance computer systems. In parallel, exponentially increasing power density and packaging costs have ne...
Ramkumar Jayaseelan, Tulika Mitra