555 search results - page 1 / 111 » Efficient event-driven simulation of parallel processor arch... |
CODES
2009
IEEE
13 years 11 months ago
2009
IEEE
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
SAMOS
2004
Springer
13 years 10 months ago
2004
Springer
In this paper we present a new approach for generating high-speed optimized event-driven register transfer level (RTL) compiled simulators. The generation of the simulators is part...
SCOPES
2007
Springer
13 years 11 months ago
2007
Springer
CG
2008
Springer
13 years 5 months ago
2008
Springer
As multi-core processor systems become more and more widespread, the demand for efficient parallel algorithms also propagates into the field of computer graphics. This is especial...
DAC
2010
ACM
13 years 8 months ago
2010
ACM
Fault simulation is essential in test generation, design for test and reliability assessment of integrated circuits. Reliability analysis and the simulation of self-test structure...