13 search results - page 3 / 3 » Efficient exploration of on-chip bus architectures and memor... |
ICCD
1999
IEEE
13 years 9 months ago
1999
IEEE
This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compresse...
DAC
2003
ACM
13 years 10 months ago
2003
ACM
The increasing use of microprocessor cores in embedded systems as well as mobile and portable devices creates an opportunity for customizing the cache subsystem for improved perfo...
DAC
2000
ACM
14 years 5 months ago
2000
ACM
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...