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» Efficient multi-ported memories for FPGAs
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DATE
2010
IEEE
168views Hardware» more  DATE 2010»
13 years 10 months ago
A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs
Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new...
Luca Sterpone, Niccolò Battezzati
TVLSI
2010
12 years 11 months ago
Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters
There is a dramatic logic density gap between FPGAs and ASICs, and this gap is the main reason FPGAs are not cost-effective in high volume applications. Modern FPGAs narrow this ga...
Peter A. Jamieson, Jonathan Rose
CODES
2008
IEEE
13 years 11 months ago
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs
Modern embedded compute platforms increasingly contain both microprocessors and field-programmable gate arrays (FPGAs). The FPGAs may implement accelerators or other circuits to s...
David Sheldon, Frank Vahid
FPGA
2010
ACM
181views FPGA» more  FPGA 2010»
13 years 8 months ago
Efficient multi-ported memories for FPGAs
Multi-ported memories are challenging to implement with FPGAs since the provided block RAMs typically have only two ports. We present a thorough exploration of the design space of...
Charles Eric LaForest, J. Gregory Steffan
FPL
2010
Springer
148views Hardware» more  FPL 2010»
13 years 2 months ago
FEM: A Step Towards a Common Memory Layout for FPGA Based Accelerators
FPGA devices are mostly utilized for customized application designs with heavily pipelined and aggressively parallel computations. However, little focus is normally given to the FP...
Muhammad Shafiq, Miquel Pericàs, Nacho Nava...