Sciweavers

5 search results - page 1 / 1
» Efficient test-data compression for IP cores using multileve...
Sort
View
DATE
2006
IEEE
84views Hardware» more  DATE 2006»
13 years 11 months ago
Efficient test-data compression for IP cores using multilevel Huffman coding
Xrysovalantis Kavousianos, Emmanouil Kalligeros, D...
ICCAD
2007
IEEE
109views Hardware» more  ICCAD 2007»
13 years 8 months ago
CacheCompress: a novel approach for test data compression with cache for IP embedded cores
Abstract-- In this paper, we propose a novel test data compression technique named CacheCompress, which combines selective encoding and dynamic dictionary based encoding. Depending...
Hao Fang, Chenguang Tong, Bo Yao, Xiaodi Song, Xu ...
VLSID
2005
IEEE
131views VLSI» more  VLSID 2005»
14 years 5 months ago
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Sh...
DATE
2008
IEEE
126views Hardware» more  DATE 2008»
13 years 6 months ago
State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores
1 We present a new type of Linear Feedback Shift Registers, State Skip LFSRs. State Skip LFSRs are normal LFSRs with the addition of a small linear circuit, the State Skip circuit,...
V. Tenentes, Xrysovalantis Kavousianos, Emmanouil ...
DATE
2003
IEEE
134views Hardware» more  DATE 2003»
13 years 10 months ago
A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration
The design of high performance multimedia systems in a short time force us to use IP's blocks in many designs. However, their correct integration in a design implies more com...
Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Ri...