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DATE
2007
IEEE
102views Hardware» more  DATE 2007»
13 years 11 months ago
Efficient testbench code synthesis for a hardware emulator system
: - The rising complexity of modern embedded systems is causing a significant increase in the verification effort required by hardware designers and software developers, leading to...
Ioannis Mavroidis, Ioannis Papaefstathiou
ISSS
2000
IEEE
144views Hardware» more  ISSS 2000»
13 years 9 months ago
Efficient Hardware Controller Synthesis for Synchronous Dataflow Graph in System Level Design
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification in system level design. In the presented design methodology, each node of a data flow gra...
Hyunuk Jung, Kangnyoung Lee, Soonhoi Ha
RSP
1999
IEEE
160views Control Systems» more  RSP 1999»
13 years 9 months ago
Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping
SDL is currently gaining interest as a system level specification language for HW/SW codesign. Automated synthesis of SDL in hardware so far had problems with its efficiency. The ...
Oliver Bringmann, Wolfgang Rosenstiel, Annette Mut...
CODES
2006
IEEE
13 years 8 months ago
Increasing hardware efficiency with multifunction loop accelerators
To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
SOSP
1989
ACM
13 years 6 months ago
Threads and Input/Output in the Synthesis Kernel
The Synthesis operating system kernel combines several techniques to provide high performa.nce, incl1iding kernel code synthesis, fine-gra.in scheduling. and optimistic sylicllrol...
Henry Massalin, Calton Pu