15 search results - page 2 / 3 » Efficient timing closure without timing driven placement and... |
DAC
2007
ACM
14 years 5 months ago
2007
ACM
Abstract-- In nanometer-scale VLSI technologies, several interconnect issues like routing congestion and interconnect delay have become the main concerns in placement. However, all...
ISPD
1997
ACM
13 years 8 months ago
1997
ACM
- This paper reports on a highly effective methodology to construct complex high performance microprocessors. Critical aspects of the methodology include an integrated database for...
DAC
2008
ACM
14 years 5 months ago
2008
ACM
Due to skewed scaling of interconnect delay and cell delay with technology scaling, modern VLSI timing closure requires use of extensive buffer insertion. Inserting a large number...
ISPD
2009
ACM
13 years 11 months ago
2009
ACM
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
In this paper, we show that under the constant delay model the placement problem is equivalent to minimizing a weighted sum of wire lengths. The weights can be efficiently compute...