135 search results - page 1 / 27 » Efficient tree topology for FPGA interconnect network |
GLVLSI
2008
IEEE
13 years 5 months ago
2008
IEEE
This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butterfly-FatTree topolo...
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents a new Multilevel hierarchical FPGA (MFPGA) architecture that unifies two unidirectional programmable networks: A predictible downward network based on the But...
FPGA
2003
ACM
13 years 10 months ago
2003
ACM
How does multilevel metalization impact the design of FPGA interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the thirddi...
ICCD
1994
IEEE
13 years 9 months ago
1994
IEEE
There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing devices, and software accelerators. An important part of designing such a sy...
ERSA
2006
13 years 6 months ago
2006
Abstract-- With the constantly increasing gate capacity of FPGAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, N...