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GLVLSI
2008
IEEE

Efficient tree topology for FPGA interconnect network

8 years 7 months ago
Efficient tree topology for FPGA interconnect network
This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butterfly-FatTree topology, and an upward network using hierarchy. Studies based on Rent's Rule show that switch requirements in this architecture grow slower than in traditional Mesh topologies. New tools are developed to place and route several benchmark circuits on this architecture. Experimental results show that the Tree-based architecture can implement MCNC benchmark circuits with an average gain of 54% in total area compared with Mesh architecture. Categories and Subject Descriptors B.6.1[Logic Design]: Design Styles General Terms Design, Experimentation, Performance Keywords FPGA, Hierarchy, Interconnect, Rent's rule, Routing
Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib
Added 08 Dec 2010
Updated 08 Dec 2010
Type Conference
Year 2008
Where GLVLSI
Authors Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib Mehrez
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