166 search results - page 3 / 34 » Efficient worst case timing analysis of data caching |
OTM
2004
Springer
13 years 10 months ago
2004
Springer
Cache memories are mandatory to bridge the growing gap between CPU speed and main memory access time. Standard cache organizations improve the average execution time but are diffi...
RTS
2002
13 years 5 months ago
2002
The purpose of this paper is to introduce frameworks based on data-flow equations which provide for estimating the worst-case execution time (WCET) of (real-time) programs. These f...
EMSOFT
2007
Springer
13 years 11 months ago
2007
Springer
This paper describes techniques to estimate the worst case execution time of executable code on architectures with data caches. The underlying mechanism is Abstract Interpretation...
CASES
2006
ACM
13 years 9 months ago
2006
ACM
This paper proposes an efficient method to analyze worst case interruption delay (WCID) of a workload running on modern microprocessors using a cycle accurate simulator (CAS). Our...
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
Abstract—Employing COTS components in real-time embedded systems leads to timing challenges. When multiple CPU cores and DMA peripherals run simultaneously, contention for access...