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FPL
2007
Springer
128views Hardware» more  FPL 2007»
13 years 11 months ago
Embedded Programmable Logic Core Enhancements for System Bus Interfaces
Programmable logic cores (PLCs) offer a means of providing post-fabrication re-configurability to a SoC design. Circuits implemented in a PLC will inevitably have lower timing per...
Bradley R. Quinton, Steven J. E. Wilton
DFT
1999
IEEE
114views VLSI» more  DFT 1999»
13 years 9 months ago
Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM
A programmable single-chip multiprocessor system for video coding has been developed. The system is implemented in a high-performance 0.25 m logic/embedded DRAM process. It integr...
Markus Rudack, Dirk Niggemeyer
ISCAS
2007
IEEE
103views Hardware» more  ISCAS 2007»
13 years 11 months ago
A Low-cost and High-performance SoC Design for OMA DRM2 Applications
A SoC design for applications of OMA DRM 2 Agent in mobile phones is presented in this paper, which has been verified by Altera Stratix EP1S80B956C6 FPGA development board. Several...
Yehua Gu, Xiaoyang Zeng, Jun Han, Jia Zhao
TVLSI
2008
187views more  TVLSI 2008»
13 years 4 months ago
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable applica...
Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Che...