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MJ
2006
145views more  MJ 2006»
13 years 6 months ago
A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems
In this paper, we propose a method for speeding-up Digital Signal Processing applications by partitioning them between the reconfigurable hardware blocks of different granularity ...
Michalis D. Galanis, Athanasios Milidonis, Athanas...
FCCM
2002
IEEE
126views VLSI» more  FCCM 2002»
13 years 11 months ago
Hyperspectral Image Compression on Reconfigurable Platforms
NASA’s satellites currently do not make use of advanced image compression techniques during data transmission to earth because of limitations in the available platforms. With th...
Thomas W. Fry, Scott Hauck
FPGA
2001
ACM
152views FPGA» more  FPGA 2001»
13 years 10 months ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
Jörg Ritter, Paul Molitor
IAJIT
2008
191views more  IAJIT 2008»
13 years 6 months ago
Novel Image Compression Using Multiwavelets with SPECK Algorithm
: Compression is the process of representing information in a compact form so as to reduce the bit rate for transmission or storage while maintaining acceptable fidelity or data qu...
Sudhakar Radhakrishnan, Jayaraman Subramaniam
ICIP
1999
IEEE
14 years 7 months ago
Quadtrees for Embedded Surface Visualization: Constraints and Efficient Data Structures
The quadtree data structure is widely used in digital image processing and computer graphics for modeling spatial segmentation of images and surfaces. A quadtree is a tree in whic...
Laurent Balmelli, Jelena Kovacevic, Martin Vetterl...