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» Embedded system synthesis under memory constraints
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CORR
2006
Springer
112views Education» more  CORR 2006»
13 years 5 months ago
High-level synthesis under I/O Timing and Memory constraints
The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper...
Philippe Coussy, Gwenolé Corre, Pierre Bome...
ISSS
1996
IEEE
169views Hardware» more  ISSS 1996»
13 years 10 months ago
The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems
The application range of the embedded computing is going to cover the majority of the market products spanning from consumer electronic, automotive, telecom and process control. F...
Alessandro Balboni, William Fornaciari, M. Vincenz...
ICCAD
1994
IEEE
137views Hardware» more  ICCAD 1994»
13 years 10 months ago
Dynamic scheduling and synchronization synthesis of concurrent digital systems under system-level constraints
We present in this paper a novel control synthesis technique for system-level specifications that are better described as a set of concurrent synchronous descriptions, their synch...
Claudionor José Nunes Coelho Jr., Giovanni ...
ASAP
2004
IEEE
171views Hardware» more  ASAP 2004»
13 years 9 months ago
CHARMED: A Multi-Objective Co-Synthesis Framework for Multi-Mode Embedded Systems
In this paper, we present a modular co-synthesis framework called CHARMED that solves the problem of hardware-software co-synthesis of periodic, multi-mode, distributed, embedded ...
Vida Kianzad, Shuvra S. Bhattacharyya
ASPDAC
2008
ACM
94views Hardware» more  ASPDAC 2008»
13 years 7 months ago
Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival
A major trend in a modern system-on-chip design is a growing system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architec...
Sujan Pandey, Rolf Drechsler