4 search results - page 1 / 1 » Energy Bounds for Fault-Tolerant Nanoscale Designs |
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
- The problem of determining lower bounds for the energy cost of a given nanoscale design is addressed via a complexity theory-based approach. This paper provides a theoretical fra...
DSN
2005
IEEE
13 years 10 months ago
2005
IEEE
It is now widely accepted that the CMOS technology implementing irreversible logic will hit a scaling limit beyond 2016, and that the increased power dissipation is a major limiti...
ISLPED
2007
ACM
13 years 6 months ago
2007
ACM
Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) ...
ISCA
2011
IEEE
12 years 8 months ago
2011
IEEE
With technology scaling, manufacture-time and in-field permanent faults are becoming a fundamental problem. Multi-core architectures with spares can tolerate them by detecting an...