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ISCA
2011
IEEE
271views Hardware» more  ISCA 2011»
12 years 9 months ago
CRIB: consolidated rename, issue, and bypass
Conventional high-performance processors utilize register renaming and complex broadcast-based scheduling logic to steer instructions into a small number of heavily-pipelined exec...
Erika Gunadi, Mikko H. Lipasti
ICS
2005
Tsinghua U.
13 years 11 months ago
Low-power, low-complexity instruction issue using compiler assistance
In an out-of-order issue processor, instructions are dynamically reordered and issued to function units in their dataready order rather than their original program order to achiev...
Madhavi Gopal Valluri, Lizy Kurian John, Kathryn S...
ICCD
2006
IEEE
312views Hardware» more  ICCD 2006»
14 years 2 months ago
A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals
— Leakage power dissipation becomes a dominant component in operation power in nanometer devices. This paper describes a design methodology to implement runtime power gating in a...
Kimiyoshi Usami, Naoaki Ohkubo
CDES
2006
240views Hardware» more  CDES 2006»
13 years 7 months ago
Design of Low Power 4-Tap 8-Bit Adiabatic FIR Filter
Abstract-- Digital signal processing (DSP) is used to perform filtering, decimation and down conversion in common communications systems, like in oversampling analog to digital con...
Arun N. Chandorkar, Gurvinder Singh
HPCA
2006
IEEE
14 years 6 months ago
Software-hardware cooperative memory disambiguation
In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buf...
Ruke Huang, Alok Garg, Michael C. Huang