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» Enhanced Code Compression for Embedded RISC Processors
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DAC
1998
ACM
14 years 6 months ago
Code Compression for Embedded Systems
Memory is one of the most restricted resources in many modern embedded systems. Code compression can provide substantial savings in terms of size. In a compressed code CPU, a cach...
Haris Lekatsas, Wayne Wolf
TCAD
1998
159views more  TCAD 1998»
13 years 5 months ago
Code density optimization for embedded DSP processors using data compression techniques
We address the problem of code size minimization in VLSI systems with embedded DSP processors. Reducing code size reduces the production cost of embedded systems. We use data comp...
Stan Y. Liao, Srinivas Devadas, Kurt Keutzer
SBACPAD
2009
IEEE
155views Hardware» more  SBACPAD 2009»
14 years 6 days ago
SPARC16: A New Compression Approach for the SPARC Architecture
RISC processors can be used to face the ever increasing demand for performance required by embedded systems. Nevertheless, this solution comes with the cost of poor code density. ...
Leonardo Luiz Ecco, Bruno Cardoso Lopes, Eduardo C...
FPGA
2007
ACM
150views FPGA» more  FPGA 2007»
13 years 11 months ago
FPGA-friendly code compression for horizontal microcoded custom IPs
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
Bita Gorjiara, Daniel Gajski
CASES
2001
ACM
13 years 9 months ago
Heads and tails: a variable-length instruction format supporting parallel fetch and decode
Abstract. Existing variable-length instruction formats provide higher code densities than fixed-length formats, but are ill-suited to pipelined or parallel instruction fetch and de...
Heidi Pan, Krste Asanovic