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» Enhancing Silicon Debug via Periodic Monitoring
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DFT
2008
IEEE
86views VLSI» more  DFT 2008»
10 years 9 months ago
Enhancing Silicon Debug via Periodic Monitoring
Scan-based debug methods give high observability of internal signals, however, they require halting the system to scan out responses from the circuit-under-debug (CUD). This is ti...
Joon-Sung Yang, Nur A. Touba
ICCD
2006
IEEE
123views Hardware» more  ICCD 2006»
10 years 11 months ago
Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug
Abstract— This paper presents techniques that enhance automatically generated hardware assertion checkers to facilitate debugging within the assertion-based verification paradig...
Marc Boule, Jean-Samuel Chenard, Zeljko Zilic
DATE
2009
IEEE
110views Hardware» more  DATE 2009»
10 years 9 months ago
Trace signal selection for visibility enhancement in post-silicon validation
Today’s complex integrated circuit designs increasingly rely on post-silicon validation to eliminate bugs that escape from presilicon verification. One effective silicon debug ...
Xiao Liu, Qiang Xu
ICDE
2006
IEEE
174views Database» more  ICDE 2006»
10 years 9 months ago
The Center for Plasma Edge Simulation Workflow Requirements
The Center for Plasma Edge Simulation (CPES) is a recently funded prototype Fusion Simulation Project, which is part of the DOE SciDAC program. Our center is developing a novel in...
Scott Klasky, Bertram Ludäscher, Manish Paras...
SIGMETRICS
2009
ACM
103views Hardware» more  SIGMETRICS 2009»
10 years 9 months ago
Restrained utilization of idleness for transparent scheduling of background tasks
A common practice in system design is to treat features intended to enhance performance and reliability as low priority tasks by scheduling them during idle periods, with the goal...
Ningfang Mi, Alma Riska, Xin Li, Evgenia Smirni, E...
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