27 search results - page 4 / 6 » Estimation of Average Switching Activity in Combinational an... |
APCCAS
2006
IEEE
14 years 5 days ago
2006
IEEE
— A data driven approach to design and optimization of low power combinational multipliers is presented. This technique depends on signal gating to avoid un-necessary computation...
ICCAD
2010
IEEE
13 years 4 months ago
2010
IEEE
Reducing circuit's peak current plays an important role in circuit reliability in deep sub-micron era. For sequential circuits, it is observed that the peak current has a str...
ISLPED
1997
ACM
13 years 10 months ago
1997
ACM
We present an algorithm that restructures the state transition graph STG of a sequential circuit so as to reduce power dissipation. The STG is modi ed without changing the behav...
TCAD
1998
13 years 5 months ago
1998
In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the noti...
ICCAD
1997
IEEE
13 years 10 months ago
1997
IEEE
High-level power estimation, when given only a high-level design specification such as a functional or RTL description, requires high-level estimation of the circuit average acti...