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» Evaluating Bufferless Flow Control for On-chip Networks
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CAL
2008
13 years 11 months ago
BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...
I. Walter, Israel Cidon, Avinoam Kolodny
INFOCOM
2005
IEEE
14 years 4 months ago
Connection admission control for flow level QoS in bufferless models
Abstract— Admission control algorithms used in access networks for multiplexed voice sources are typically based on aggregated system characteristics, such as aggregate loss prob...
Sándor Rácz, Tamás Jakabfy, J...
ISCA
2009
IEEE
192views Hardware» more  ISCA 2009»
14 years 5 months ago
A case for bufferless routing in on-chip networks
Buffers in on-chip networks consume significant energy, occupy chip area, and increase design complexity. In this paper, we make a case for a new approach to designing on-chip in...
Thomas Moscibroda, Onur Mutlu
ERSA
2006
161views Hardware» more  ERSA 2006»
14 years 4 days ago
A Parametric Study of Scalable Interconnects on FPGAs
Abstract-- With the constantly increasing gate capacity of FPGAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, N...
Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Mic...
PAM
2012
Springer
12 years 6 months ago
OFLOPS: An Open Framework for OpenFlow Switch Evaluation
Recent efforts in software-defined networks, such as OpenFlow, give unprecedented access into the forwarding plane of networking equipment. When building a network based on OpenFl...
Charalampos Rotsos, Nadi Sarrar, Steve Uhlig, Rob ...