79 search results - page 2 / 16 » Evaluating Bufferless Flow Control for On-chip Networks |
CAL
2008
13 years 11 months ago
2008
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...
INFOCOM
2005
IEEE
14 years 4 months ago
2005
IEEE
Abstract— Admission control algorithms used in access networks for multiplexed voice sources are typically based on aggregated system characteristics, such as aggregate loss prob...
ISCA
2009
IEEE
14 years 5 months ago
2009
IEEE
Buffers in on-chip networks consume significant energy, occupy chip area, and increase design complexity. In this paper, we make a case for a new approach to designing on-chip in...
ERSA
2006
14 years 4 days ago
2006
Abstract-- With the constantly increasing gate capacity of FPGAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, N...
PAM
2012
Springer
12 years 6 months ago
2012
Springer
Recent efforts in software-defined networks, such as OpenFlow, give unprecedented access into the forwarding plane of networking equipment. When building a network based on OpenFl...