38 search results - page 2 / 8 » Evaluating Fault Emulation on FPGA |
DSD
2005
IEEE
13 years 11 months ago
2005
IEEE
Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation is an important subta...
DSN
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper presents an experimental study on the emulation of software faults by fault injection. In a first experiment, a set of real software faults has been compared with fault...
FPGA
2003
ACM
13 years 10 months ago
2003
ACM
This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has bee...
ICCD
2008
IEEE
14 years 2 months ago
2008
IEEE
— Extreme scaling practices in silicon technology are quickly leading to integrated circuit components with limited reliability, where phenomena such as early-transistor failures...
ASAP
2007
IEEE
13 years 7 months ago
2007
IEEE
Interconnect validation is an important early step toward global SoC (System-On-Chip) validation. Fast performances evaluation and design space exploration for NoCs (Networks-On-C...