169 search results - page 2 / 34 » Evaluation of Error-Resilience for Reliable Compression of T... |
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
1 The low throughput at IC (Integrated Circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (Automatic Test Equipment) memory requirements and...
DAC
2005
ACM
13 years 6 months ago
2005
ACM
This paper presents a new test response compaction technique with any number of unknown logic values (X’s) in the test response bits. The technique leverages an X-tolerant respo...
DAC
2003
ACM
13 years 10 months ago
2003
ACM
We propose in this paper an extension on the Scan Chain Concealment technique to further reduce test time and volume requirement. The proposed methodology stems from the architect...
ATS
2010
IEEE
12 years 12 months ago
2010
IEEE
In recent technology nodes, reliability is considered a part of the standard design flow at all levels of embedded system design. While techniques that use only low-level models at...
ICIP
2000
IEEE
14 years 6 months ago
2000
IEEE
In this paper, a comparative study of lossless compression algorithms is presented. The following algorithms are considered: UNIX compress, gzip, LZW, CCITT Group 3 and Group 4, J...