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» Evaluation of a Hierarchical Shaper as a Policy Execution Po...
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CF
2004
ACM
10 years 10 months ago
Predictable performance in SMT processors
Current instruction fetch policies in SMT processors are oriented towards optimization of overall throughput and/or fairness. However, they provide no control over how individual ...
Francisco J. Cazorla, Peter M. W. Knijnenburg, Riz...
ICS
2009
Tsinghua U.
10 years 2 months ago
Refereeing conflicts in hardware transactional memory
In the search for high performance, most transactional memory (TM) systems execute atomic blocks concurrently and must thus be prepared for data conflicts. The TM system must then...
Arrvindh Shriraman, Sandhya Dwarkadas
IEEEPACT
2009
IEEE
10 years 11 months ago
Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors
Translation Lookaside Buffers (TLBs) are a staple in modern computer systems and have a significant impact on overall system performance. Numerous prior studies have addressed TL...
Abhishek Bhattacharjee, Margaret Martonosi
MOBISYS
2011
ACM
9 years 7 months ago
Odessa: enabling interactive perception applications on mobile devices
Resource constrained mobile devices need to leverage computation on nearby servers to run responsive applications that recognize objects, people, or gestures from real-time video....
Moo-Ryong Ra, Anmol Sheth, Lily B. Mummert, Padman...
ICSEA
2007
IEEE
10 years 10 months ago
An Access Control Metamodel for Web Service-Oriented Architecture
— With the mutual consent to use WSDL (Web Service Description Language) to describe web service interfaces and SOAP as the basic communication protocol, the cornerstone for web ...
Christian Emig, Frank Brandt, Sebastian Abeck, J&u...
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