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» Exact and fast L1 cache simulation for embedded systems
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ASPDAC
2009
ACM
111views Hardware» more  ASPDAC 2009»
13 years 11 months ago
Exact and fast L1 cache simulation for embedded systems
Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tat...
ISSS
2002
IEEE
151views Hardware» more  ISSS 2002»
13 years 9 months ago
Tuning of Loop Cache Architectures to Programs in Embedded System Design
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
Frank Vahid, Susan Cotterell
GECCO
2004
Springer
148views Optimization» more  GECCO 2004»
13 years 10 months ago
A Multi-objective Approach to Configuring Embedded System Architectures
Portable embedded systems are being driven by consumer demands to be thermally efficient, perform faster, and have longer battery life. To design such a system, various hardware un...
James Northern III, Michael A. Shanblatt
RTAS
2005
IEEE
13 years 10 months ago
Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
Harini Ramaprasad, Frank Mueller
IESS
2009
Springer
182views Hardware» more  IESS 2009»
13 years 2 months ago
Modeling Cache Effects at the Transaction Level
Abstract. Embedded system design complexities are growing exponentially. Demand has increased for modeling techniques that can provide both accurate measurements of delay and fast ...
Ardavan Pedram, David Craven, Andreas Gerstlauer