87 search results - page 2 / 18 » Exploiting Instruction Redundancy for Transient Fault Tolera... |
ISCA
2003
IEEE
13 years 11 months ago
2003
IEEE
To address the increasing susceptibility of commodity chip multiprocessors (CMPs) to transient faults, we propose Chiplevel Redundantly Threaded multiprocessor with Recovery (CRTR...
DSN
2005
IEEE
13 years 7 months ago
2005
IEEE
The increasing transient fault rate will necessitate onchip fault tolerance techniques in future processors. The speed gap between the processor and the memory is also increasing,...
ISCA
2005
IEEE
13 years 11 months ago
2005
IEEE
CMOS scaling increases susceptibility of microprocessors to transient faults. Most current proposals for transient-fault detection use full redundancy to achieve perfect coverage ...
ISCA
2002
IEEE
13 years 10 months ago
2002
IEEE
We propose a scheme for transient-fault recovery called Simultaneously and Redundantly Threaded processors with Recovery (SRTR) that enhances a previously proposed scheme for tran...
ASPDAC
2005
ACM
13 years 7 months ago
2005
ACM
In this paper we propose a fault-tolerant processor architecture and an associated fault-tolerant computation model capable of fault tolerance in the nanoelectronic environment th...