9 search results - page 1 / 2 » Exploiting Loop-Level Parallelism on Coarse-Grained Reconfig... |
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
APCSAC
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper introduces a method which can be used to map applications written in a high level source language program, like C, to a coarse grain reconfigurable architecture, MONTIU...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
This paper shows that software pipelining can be an effective technique for code generation for coarse-grained reconfigurable instruction set processors. The paper describes a tec...
IPPS
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper presents a compiler methodology for memoryaware mapping on 2-Dimensional coarse-grained reconfigurable architectures that aims in improving the mapped applications’ p...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...